Circuits and Methods for a Noise Shaping Analog To Digital Converter

ABSTRACT

Systems and methods are provided for analog-to-digital conversion (ADC). A first quantization stage may be configured to receive an analog input signal and sample the analog input signal to generate a first digital signal, the first quantization stage may be further configured to filter the first digital signal with a first noise-shaping transfer function to generate a first noise-shaped digital output and to generate a quantization error signal based on a comparison of the analog input signal and the first noise-shaped digital output. A voltage controlled oscillator (VCO)-based second quantization stage may be configured to receive the quantization error signal and sample the quantization error signal to generate a second digital signal, the VCO-based second quantization stage may be further configured to filter the second digital signal with a second noise-shaping transfer function to generate a second noise-shaped digital output. A first digital filter may be configured to filter the first noise-shaped digital output with an equivalent signal transfer function of the VCO-based second quantization stage to generate a first stage digital output. A second digital filter may be configured to filter the second noise-shaped digital output with the first noise-shaping transfer function to generate a second stage digital output with second order noise-shaping characteristics A combination circuit may combine the first stage digital output and the second stage digital output to generate a digital ADC output signal with second order noise shaping characteristics.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.17/718,467, filed Apr. 12, 2022, which claims priority to U.S.Provisional Application No. 63/281,790, filed Nov. 22, 2021, each ofwhich is incorporated herein by reference in their entirety.

TECHNICAL FIELD

The technology described in this patent document relates generally toanalog to digital converters.

BACKGROUND

An analog-to-digital converter (ADC) is usable to convert analog signalsto digital signals. An ADC structure typically includes one or morequantizers, which map a continuous analog signal to discrete digitalrepresentations using a quantization process such as rounding ortruncation. The quantization process typically introduces an error,commonly referred to as quantization error, that results from mapping acontinuous input signal to a finite set of discrete quantization levels.Voltage controlled oscillator (VCO)-based quantizers are known to reducequantization error because a VCO has inherent first order noise shapingof its quantization error. A VCO, however, typically suffers fromvoltage-to-frequency tuning curve (i.e., VCO tuning gain) non-linearity,which may limit the signal-to-(noise+distortion) ratio (SNDR) of atypical VCO-based quantizer.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures.

FIG. 1 is a block diagram of an example analog-to-digital conversioncircuit in accordance with embodiments.

FIG. 2 is a signal flow diagram of an example embodiment of ananalog-to-digital circuit in accordance with embodiments.

FIG. 3 is a signal flow diagram of another example embodiment of ananalog-to-digital circuit in accordance with embodiments.

FIG. 4 is a flow diagram of an example analog-to-digital conversionmethod in accordance with embodiments.

FIGS. 5A-5C are signal diagrams showing an example frequency-domainoperation of the analog-to-digital circuit shown in FIG. 2 .

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in some various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween some various embodiments and/or configurations discussed.

FIG. 1 is a block diagram of an example analog-to-digital conversion(ADC) circuit 100 with second order noise shaping in accordance withembodiments. The example ADC circuit 100 includes a first quantizationstage 102, a second quantization stage 104, a first digital filter 106,a second digital filter 108, and a combination circuit 110.

The first quantization stage 102 is configured to receive an analoginput signal (X₁) 112, sample the analog input signal 112 to generate adigital signal, and filter the digital signal with a first noise-shapingtransfer function (NTF₁) to generate a first noise-shaped digital output(y₁₁) 114. The first quantization stage 102 is further configured togenerate a quantization error signal (q₁) based, at least in part, on acomparison of the analog input signal 112 and the digital output 114. Inembodiments, the first quantization stage 102 may include a successiveapproximation register (SAR) quantizer that utilizes the quantizationerror signal (q₁) in a feedback loop to the analog input signal 112, forexample as described below with reference to the example shown in FIG. 2. A SAR-based first quantization stage may, for example, determine thequantization error signal (q₁) based on a residue voltage produced bythe SAR quantizer during generation of the first noise-shaped digitaloutput, and may shape the quantization error signal (q₁) using a loopfilter to achieve predetermined noise-shaping characteristics having anoise-shaping transfer function (NTF₁).

The second quantization stage 104 may be a voltage controlled oscillator(VCO)-based quantization stage that is configured to receive aninversion of the quantization error signal (−q₁) 116 and sample theinverted quantization error signal (−q₁) to generate a second digitalsignal. The VCO-based second quantization stage 104 may be furtherconfigured to filter the second digital signal with a secondnoise-shaping transfer function (NTF₂) to generate a second noise-shapeddigital output (y₂₁) 118. In embodiments, the VCO-based quantizationstage 104 may include an open-loop quantizer configuration (i.e.,without a feedback loop) in which the noise-shaping transfer function(NTF₂) approximates a first-order difference operation, for example asdescribed below with reference to the example shown in FIG. 2 .

The first digital filter 106 is configured to filter the firstnoise-shaped digital output (y₁₁) 114 with a signal transfer function(STF₂) of the second quantization stage 104 in order to match thefiltering function seen by the first stage quantization error containedin both y₂₁ and y₂₂ paths. The second digital filter 108 is configuredto filter the second noise-shaped digital output y₍₂₁₎ 118 with thenoise-shaping transfer function (NTF₁) of the first quantization stage102 to generate a second stage digital output (y₂₂) 120 with secondorder noise-shaping characteristics. The combination circuit 110 in theillustrated embodiment is an adder circuit that combines the first stagedigital output (y₁₂) 120 and the second stage digital output (y₂₂) togenerate a digital ADC output signal (Y₀) 122 with second order noiseshaping characteristics. In other embodiments, the combination circuit110 may, for example, be a difference circuit and the quantizationsignal input 116 to the second quantization stage 104 may benon-inverted.

FIG. 2 is a signal flow diagram of an example embodiment of ananalog-to-digital conversion (ADC) circuit 200 in accordance withembodiments. The example ADC circuit 200 includes a noise-shaping SARquantization stage 202, an open-loop noise-shaping VCO-basedquantization stage 204, a first digital filter 206, a second digitalfilter 208, a pair of amplifiers 210, 212, and a combination circuit214.

The noise-shaping SAR quantization stage 202 receives an analog inputsignal (X₁) 216, samples the analog input signal 216 to generate adigital signal, and filters the digital signal with a firstnoise-shaping transfer function (NTF₁) to generate a first noise-shapeddigital output (y₁₁) 218. The noise-shaping SAR quantization stage 202is further configured to generate a quantization error signal (q₁) 220based, at least in part, on a comparison of the analog input 228 and thedigital output 218. The quantization error signal (q₁) 220 is delayed byone clock cycle (z⁻¹) by delay block 222 and is fed back to the analoginput via combination block 224.

The noise-shaping transfer function (NTF₁) of the SAR quantization stage202 may be represented by the Z-domain expression (1−z⁻¹). Thenoise-shaped digital output (y₁₁) 218 may then be represented by theequation, y₁₁=X₁+q₁(1−z⁻¹). An example spectrum of the noise-shapeddigital output (y₁₁) 218 is illustrated in the frequency-domain signaldiagram shown in FIG. 5A. As illustrated in FIG. 5A, the noise-shapeddigital output (y₁₁) 218 does not include harmonic distortion, which istypical for a SAR quantization stage 202 having linear noise shaping.

The SAR quantization stage 202 may, for example, be implemented using aknown SAR architecture that includes switched capacitors, digital logic,and comparators, that are configured to high pass filter the comparatornoise and quantization error, thereby diminishing the noise in the lowfrequency band of interest. In embodiments, the SAR quantization stage202 may have a moderate resolution, such as a 6-bit digital output (y₁₁)218. In one embodiment, the SAR quantization stage 202 may, for example,be implemented using the SAR architecture described in U.S. patentapplication Ser. No. 17/020,219, titled “Method and Circuit for NoiseShaping SAR Analog-to-Digital Converter,” the entirety of which isincorporated herein by reference. In the illustrated signal flow diagram200, the SAR quantization is depicted by SAR block 226 and thequantization error (q₁) that is inherent to the SAR quantization processis depicted as an input to block 226 (i.e., quantization error (q₁) isnot an actual physical input to quantization block 226). In addition,the illustrated signal flow diagram 200 depicts the comparison of theanalog input 228 and the digital output 216 to generate quantizationerror signal (q₁) 220 using comparison block 230. It should beunderstood, however, that in a SAR architecture the quantization error(q₁) is available at the end of the conversion cycle, i.e., thequantization error signal (q₁) 220 may be determined based on a residuevoltage produced by the SAR quantizer 226 during generation of thenoise-shaped digital output 218, and thus the quantization error signal(q₁) 220 may be generated without the need for additional hardware (suchas a difference circuit.)

An inverse of the quantization error signal (q₁) 220 may be amplified byamplifier 210, which provides an analog inter-stage gain (G_(A)), andthe amplified quantization error signal (−q₁·G_(A)) is input to theopen-loop noise-shaping VCO-based quantization stage 204. The signalflow diagram of the open-loop noise-shaping VCO-based quantization stage204 includes a voltage controlled oscillator (VCO) block 232, aquantizer block 234, and a first order difference block 236. The VCOblock 232 may, for example, be implemented using a multi-phase ringoscillator that is frequency modulated using the amplified quantizationerror signal (−q₁·G_(A)) input as a tuning voltage. As depicted in thesignal flow diagram at reference 242, the VCO 232 may be modelled as anintegrator that converts the input signal from the voltage domain to thephase domain and has a non-linear voltage-to-frequency tuning curve,which can be expressed as the equation k_(vco)/s, where k_(vco) is theVCO voltage-to-frequency tuning gain and “1/s” represents the Laplacetransform of the integrator. The impact of VCO non-linearity ismitigated, however, because the amplified quantization error signal(−q₁·G_(A)) input is small and mostly random in nature.

The quantizer 234 provides a quantized estimate of the input amplifiedquantization error signal (−q₁·G_(A)), for example by using a set ofregisters to count the number of oscillator edges generated by the VCOblock 232 within each period of an input clock signal (CLK) 240. In theillustrated signal flow diagram 200, the quantizer 234 is modelled as asampler that adds quantization error (q₂) 238. It should be understoodthat quantization error (q₂) 238 is an inherent property of thequantizer 234, although depicted as an input to the quantizer 234 forillustrative purposes (i.e., the quantization error (q₂) 238 is not anactual physical input to the quantizer 234).

The first order difference block 236 may, for example, include a logiccircuit that filters the output of the quantizer 234 with anoise-shaping transfer function (NTF₂) to generate a second noise-shapeddigital output (y₂₁). The second noise-shaping transfer function (NTF₂)may be expressed as (1−z⁻¹), and the noise-shaped digital output (y₂₁)244 from the VCO-based quantization stage 204 may be expressed as theequation, y₂₁=−q₁·G_(A)·2NT_(clk)k_(vco)−z⁻¹+(1−z⁻¹)q₂, where q₁ is thequantization error of the SAR quantization stage 202, G_(A) is the gainapplied by amplifier 210, N is the number of phases in the ring VCO 232,T_(clk) is the sampling clock (CLK) 240 time period, k_(vco) is the VCOvoltage-to-frequency tuning gain, and q₂ is the quantization error ofthe VCO-based quantization stage 204.

The noise-shaped digital output (y₂₁) 244 from the VCO-basedquantization stage 204 is filtered by the second digital filter 208 withthe noise-shaping transfer function (NTF₁) of the SAR quantization stage202 to generate a second stage digital output (y₂₂) 246 with secondorder noise-shaping characteristics. The second stage digital output(y₂₂) 246 may thus be expressed as the equation,y₂₂=−q₁·G_(A)·2NT_(clk)k_(vco)·z⁻¹(1−z⁻¹)+(1−z⁻¹)²q₂. An examplespectrum of the second state digital output (y₂₂) 246 is illustrated inthe frequency-domain signal diagram shown in FIG. 5B. As illustrated inFIG. 5B, the second state digital output (y₂₂) 246 does not includeharmonic distortion, which is because the input to the VCO-basedquantization stage 204 is the quantization error (q₁) from the SAR-basedquantization stage 202 (and not the analog input signal (X₁)). Theskilled artisan will recognize that the lack of harmonic distortion inthe output of the VCO-based quantization stage 204 is advantageousbecause a VCO-based quantizer often produces harmonic distortion.

In addition, the noise-shaped digital output (y₁₁) 218 from the SARquantization stage 202 is filtered by the first digital filter 206 witha signal transfer function (STF₂) of the VCO-based quantization stage204 in order match the filtering functions seen by the first stagequantization error (q₁) as it traverses both y₂₁ and y₂₂ paths. Thefirst stage digital output (y₁₂) 248 may be expressed as the equation,y₁₂=STF₂[X₁+q₁(1−z⁻¹)²].

The second stage digital output (y₂₂) 246 is scaled by the amplifier212, which may for example apply a digital gain of 1/G_(D), whereG_(D)=G_(A), such that the digital amplifier 212 removes the gain(G_(A)) applied to the input signal by the analog amplifier 210. Thedigital output (y₂₃) 250 of the digital amplifier 212 may thus beexpressed by the equation,

${y_{23} = {{{- q_{1}} \cdot {{STF}_{2}\left( {1 - z^{- 1}} \right)}} + {\left( {1 - z^{- 1}} \right)^{2}\frac{q_{2}}{G_{D}}}}},{{{where}{STF}_{2}} = {2{NT}_{clk}{k_{VCO} \cdot z^{- 1}}}}$

The combination circuit 214 in the illustrated embodiment is an addercircuit that combines the first stage digital output (y₁₂) 248 and thesecond stage digital output (y₂₃) 250 to generate a digital ADC outputsignal (Y₀) 252 with second order noise shaping characteristics. Thedigital ADC output signal (Y₀) 252 may be expressed by the equation,

$Y_{0} = {{X_{1}{STF}_{2}} + {\frac{q_{2}}{G_{D}}{\left( {1 - z^{- 1}} \right)^{2}.}}}$

In other embodiments, the combination circuit 214 may, for example, be asubtraction circuit and the quantization signal input to the analogamplifier 210 may be non-inverted.

An example spectrum of the digital ADC output signal (Y₀) 252 isillustrated in the frequency-domain signal diagram shown in FIG. 5C. Asillustrated in FIG. 5C, the digital ADC output signal (Y₀) 252 does notinclude harmonic distortion and has an increased slope compared to FIGS.5A and 5B. For instance, in the embodiment illustrated in FIG. 5C, thedigital ADC output signal (Y₀) 252 has a slope of 40 dB/dec and a SNDRof approximately 75 bB. Also illustrated in FIG. 5C is an example of anoutput signal 500 from a typical VCO-based ADC. As illustrated, theoutput from a typical VCO-based ADC includes harmonic distortion atreference 502, which is absent from the digital ADC output signal (Y₀)252.

FIG. 3 is a signal flow diagram of another example embodiment of ananalog-to-digital circuit 300 in accordance with embodiments. Theexample ADC circuit 300 includes a noise-shaping SAR quantization stage302 with a digital up-sampler 303 at the output, an open-loopnoise-shaping VCO-based quantization stage 304, a first digital filter306, a second digital filter 308, a pair of amplifiers 310, 312, and acombination circuit 314.

The noise-shaping SAR quantization stage 302 receives an analog inputsignal (X₁) 316, samples the analog input signal 316 to generate adigital signal, and filters the digital signal with a firstnoise-shaping transfer function (NTF₁) to generate a first noise-shapeddigital output (y₁₁) 318. The sampling rate of the noise-shaped output(y₁₁) 318 is then increased by a factor “m” with the digital up-sampler303. The value of “m” may, for example, be selected as a ratio of thequantization clock signals (F_(clk2)/F_(clk1)), as detailed below. Thenoise-shaping SAR quantization stage 302 is further configured togenerate a quantization error signal (q₁) 320 based, at least in part,on a comparison of the analog input 328 and the digital output 318. Thequantization error signal (q₁) 320 is delayed by one clock cycle (z⁻¹)by delay block 322 and is fed back to the analog input via combinationblock 324.

The noise-shaping transfer function (NTF₁) of the SAR quantization stage302 may be represented by the Z-domain expression (1−z⁻¹). Thenoise-shaped digital output (y₁₁) 318 may then be represented by theequation, y₁₁=X₁+q₁(1−z⁻¹).

The SAR quantization stage 302 may, for example, be implemented using aknown SAR architecture that includes switched capacitors, digital logic,and comparators, that are configured to high pass filter the comparatornoise and quantization error, thereby diminishing the noise in the lowfrequency band of interest. The SAR quantization stage 302 in thisembodiment 300 may, for example, have a reduced resolution, such as a 4or 5 bit digital output (y₁₁) 318 in order to enable a faster samplingrate.

In the illustrated signal flow diagram 300, the SAR quantization isdepicted by SAR block 326 and the quantization error (q₁) that isinherent to the SAR quantization process is depicted as an input toblock 326 (i.e., quantization error (q₁) is not an actual physical inputto quantization block 326). In addition, the illustrated signal flowdiagram 300 depicts the comparison of the analog input 328 and thedigital output 316 to generate quantization error signal (q₁) 320 usingcomparison block 330. It should be understood, however, that in a SARarchitecture the quantization error (q₁) is available at the end of theconversion cycle, i.e., the quantization error signal (q₁) 320 may bedetermined based on a residue voltage produced by the SAR quantizer 326during generation of the noise-shaped digital output 318, and thus thequantization error signal (q₁) 320 may be generated without the need foradditional hardware (such as a difference circuit.)

An inverse of the quantization error signal (q₁) 320 may be amplified byamplifier 310, which provides an analog inter-stage gain (G_(A)), andthe amplified quantization error signal (−q₁·G_(A)) is input to theopen-loop noise-shaping VCO-based quantization stage 304. The signalflow diagram of the open-loop noise-shaping VCO-based quantization stage304 includes a voltage controlled oscillator (VCO) block 332, aquantizer block 334, and a first order difference block 336. The VCOblock 332 may, for example, be implemented using a multi-phase ringoscillator that is frequency modulated using the amplified quantizationerror signal (−q₁·G_(A)) input as a tuning voltage.

The quantizer 334 provides a quantized estimate of the input amplifiedquantization error signal (−q₁·G_(A)), for example, by using a set ofregisters to count the number of oscillator edges generated by the VCOblock 332 within each period of an input clock signal (F_(CLK2)) 340. Inthis embodiment 300, input clock signal (F_(CLK2)) 340 has a higherfrequency than the input clock signal (Fclk1) 341 for the SARquantization stage 302, causing the VCO-based quantization stage 304 torun at a higher sampling rate than the SAR quantization stage 302. Thismay, for example, take advantage of the ability to run the VCO-basedquantization stage 304 at a faster rate due to its open-looparchitecture and mainly digital operation.

In the illustrated signal flow diagram 300, the quantizer 334 ismodelled as a sampler that adds quantization error (q₂) 338. It shouldbe understood, however, that quantization error (q₂) 338 is an inherentproperty of the quantizer 334, although depicted as an input to thequantizer 334 for illustrative purposes (i.e., the quantization error(q₂) 338 is not an actual physical input to the quantizer 334).

The first order difference block 336 may, for example, include a logiccircuit that filters the output of the quantizer 334 with a second anoise-shaping transfer function (NTF₂) to generate a second noise-shapeddigital output (y₂₁). The second noise-shaping transfer function (NTF₂)in this embodiment 300 may be expressed as (1−z^(−/m)), where m is theratio (F_(CLK2)/F_(CLK1)) of the SAR and VCO input clocks 340, 341. Thenoise-shaped digital output (y₂₁) 344 from the VCO-based quantizationstage 304 may therefore be expressed as the equation,y₂₁=−q₁·G_(A)·2NT_(clk)k_(vco)·z⁻¹+(1−z^(−1/m))q₂.

The noise-shaped digital output (y₂₁) 344 from the VCO-basedquantization stage 304 is filtered by the second digital filter 308 withthe noise-shaping transfer function (NTF₁) of the SAR quantization stage302 to generate a second stage digital output (y₂₂) 346 with secondorder noise-shaping characteristics. The second stage digital output(y₂₂) 346 may thus be expressed as the equation,y₂₂=−q₁·G_(A)·2NT_(clk)k_(vco)·z⁻¹(1−z⁻¹)+(1−z⁻¹)(1−z⁻¹/m)q₂. Inaddition, the up-sampled digital output from the SAR quantization stage302 is filtered by the first digital filter 306 with a signal transferfunction (STF₂) of the VCO-based quantization stage 304 in order matchthe filtering functions seen by the first stage quantization error (q₁)as it traverses both y₂₁ and y₂₂ paths such that the first stagequantization error will be cancelled and eliminated from the finaloutput Y₀. The first stage digital output (y₁₂) 348 may be expressed asthe equation, Y₁₂=STF₂[X₁+q₁(1−z⁻¹)²].

The second stage digital output (y₂₂) 346 is scaled by the amplifier312, which may for example apply a digital gain of 1/G_(D), whereG_(D)=G_(A), such that the digital amplifier 312 removes the gain(G_(A)) applied to the input signal by the analog amplifier 310. Thedigital output (y₂₃) 350 of the digital amplifier 312 may thus beexpressed by the equation,

${y_{23} = {{{- q_{1}} \cdot {{STF}_{2}\left( {1 - z^{- 1}} \right)}} + {\left( {1 - z^{- 1}} \right)\left( {1 - z^{{- 1}/m}} \right)\frac{q_{2}}{G_{D}}}}},{{{where}{STF}_{2}} = {2{NT}_{clk}{k_{VCO} \cdot {z^{- 1}.}}}}$

The combination circuit 314 in the illustrated embodiment is an addercircuit that combines the first stage digital output (y₁₂) 348 and thesecond stage digital output (y₂₃) 350 to generate a digital ADC outputsignal (Y₀) 352 with second order noise shaping characteristics. Thedigital ADC output signal (Y₀) 352 may be expressed by the equation,

$Y_{0} = {{X_{1}{STF}_{2}} + {\frac{q_{2}}{G_{D}}\left( {1 - z^{- 1}} \right){\left( {1 - z^{{- 1}/m}} \right).}}}$

In other embodiments, the combination circuit 314 may, for example, be asubtraction circuit and the quantization signal input to the analogamplifier 310 may be non-inverted.

FIG. 4 is a flow diagram of an example analog-to-digital conversionmethod 400 in accordance with embodiments. While systems forimplementing the method of FIG. 4 may take a variety of forms, themethod is described with reference to previous examples herein for easeof understanding. At 402, an analog input signal (112, 216, 316) isreceived at a first quantization stage (102, 202, 302), and the analoginput signal is sampled to generate a first digital signal, and aquantization error signal (116, 220, 320) is generated based on acomparison of the analog input signal and the first noise-shaped digitaloutput. At 404, the first digital signal is filtered with a firstnoise-shaping transfer function to generate a first noise-shaped digitaloutput (114, 218, 318).

The quantization error signal (116, 220, 320) is received at a voltagecontrolled oscillator (VCO)-based second quantization stage (104, 204,304) at 406, and the quantization error signal is sampled to generate asecond digital signal. At 408, the second digital signal is filteredwith a second noise-shaping transfer function to generate a secondnoise-shaped digital output (118, 244, 344).

At 410, the first noise-shaped digital output (114, 218, 318) isfiltered (106, 206, 306) with an equivalent signal transfer function ofthe VCO-based second quantization stage (104, 204, 304) to enable thecancellation of the first stage quantization error from the final outputY₀. and generate a first stage digital output (120, 248, 348). At 412,the second noise-shaped digital output (118, 244, 344) is filtered )108,208, 308) with the first noise-shaping transfer function to generate asecond stage digital output (120, 246, 346) with second ordernoise-shaping characteristics. The first stage digital output (120, 248,348) and the second stage digital output (120, 246, 346) are combined at414 to generate a digital ADC output signal (122, 252, 352) with secondorder noise shaping characteristics.

The disclosed ADC circuit embodiments provide second order noiseshaping, as detailed above. In addition, embodiments of the disclosureare amenable to implementation in deep nano-scale technology (e.g., N3,N2) at low core supply voltage. For example, embodiments of thedisclosed SAR quantization stage work well at low supply voltage, andthe disclosed VCO-based quantization stage processes the analog input inthe time domain instead of the voltage domain, and thus may operate atlow supply voltage in advance process technologies. In addition,embodiments of the disclosed ADC circuits allow for SAR decision errorsto be absorbed by the VCO-based quantizer stage because the quantizationerror (q₁) from the SAR quantizer stage is not too large to cause VCOphase overflow. In embodiments, this may relax SAR comparator and DACsettling specifications, and eliminate a need for redundant capacitorsand/or other correction techniques. In addition, embodiments of thedisclosure may significantly mitigate the impact of VCO tuning gainnon-linearity, which mitigates any harmonic distortion that wouldotherwise be present. Further, embodiments of the disclosed ADC circuitsmay operate in a pipelined fashion to increase conversion throughputbecause the VCO-based quantization stage does not need to be stoppedbetween conversions.

Systems and methods as described herein may take a variety of forms. Inone example, systems and methods are provided for an analog-to-digitalconversion (ADC) circuit that includes a first quantization stageconfigured to receive an analog input signal and sample the analog inputsignal to generate a first digital signal, the first quantization stagefurther configured to filter the first digital signal with a firstnoise-shaping transfer function to generate a first noise-shaped digitaloutput and to generate a quantization error signal based on a comparisonof the analog input signal and the first noise-shaped digital output. Avoltage controlled oscillator (VCO)-based second quantization stage isconfigured to receive the quantization error signal and sample thequantization error signal to generate a second digital signal, theVCO-based second quantization stage further configured to filter thesecond digital signal with a second noise-shaping transfer function togenerate a second noise-shaped digital output. A first digital filter isconfigured to filter the first noise-shaped digital output with anequivalent signal transfer function of the VCO-based second quantizationstage to generate a first stage digital output, a second digital filteris configured to filter the second noise-shaped digital output with thefirst noise-shaping transfer function to generate a second stage digitaloutput with second order noise-shaping characteristics, and acombination circuit is configured to combine the first stage digitaloutput and the second stage digital output to generate a digital ADCoutput signal with second order noise shaping characteristics.

In another example, an analog-to-digital conversion (ADC) circuitincludes a first quantization stage configured to receive an analoginput signal and sample the analog input signal based on a first inputclock signal to generate a first digital signal, the first quantizationstage further configured to filter the first digital signal with a firstnoise-shaping transfer function to generate a first noise-shaped digitaloutput and to generate a quantization error signal based on a comparisonof the analog input signal and the first noise-shaped digital output. Avoltage controlled oscillator (VCO)-based second quantization stage isconfigured to receive the quantization error signal and sample thequantization error signal based on a second input clock signal togenerate a second digital signal, wherein the second input clock signalhas a higher frequency than the first input clock frequency, theVCO-based second quantization stage being further configured to filterthe second digital signal with a second noise-shaping transfer functionto generate a second noise-shaped digital output. A digital up-sampleris configured to increase a sampling rate of the first noise-shapeddigital output to generate an up-sampled digital output. A first digitalfilter is configured to filter the up-sampled digital output with anequivalent signal transfer function of the VCO-based second quantizationstage to generate a first stage digital output, a second digital filteris configured to filter the second noise-shaped digital output with thefirst noise-shaping transfer function to generate a second stage digitaloutput with second order noise-shaping characteristics, and acombination circuit is configured to combine the first stage digitaloutput and the second stage digital output to generate a digital ADCoutput signal with second order noise shaping characteristics.

As a further example, an analog-to-digital conversion (ADC) methodincludes receiving an analog input signal at a first quantization stage,and sampling the analog input signal to generate a first digital signal.A quantization error signal is generated at the first quantization stagebased on a comparison of the analog input signal and the firstnoise-shaped digital output. The first digital signal is filtered with afirst noise-shaping transfer function to generate a first noise-shapeddigital output. The quantization error signal is received at a voltagecontrolled oscillator (VCO)-based second quantization stage, andsampling the quantization error signal to generate a second digitalsignal, the second digital signal is filtered with a secondnoise-shaping transfer function to generate a second noise-shapeddigital output. The first noise-shaped digital output is filtered withan equivalent signal transfer function of the VCO-based secondquantization stage to generate a first stage digital output. The secondnoise-shaped digital output is filtered with the first noise-shapingtransfer function to generate a second stage digital output with secondorder noise-shaping characteristics, and the first stage digital outputand the second stage digital output are combined to generate a digitalADC output signal with second order noise shaping characteristics.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

1. A circuit comprising: a first quantization stage configured toreceive a quantization error signal, to sample the quantization errorsignal, to generate a first digital signal, to filter the first digitalsignal, and to generate a first noise-shaped digital output; and a firstdigital filter configured to filter the first noise-shaped digitaloutput and to generate a first stage digital output.
 2. The circuit ofclaim 1, wherein the first quantization stage includes an open loopvoltage controlled oscillator (VCO)-based quantizer.
 3. The circuit ofclaim 1, further comprising a second quantization stage configured toreceive an analog input signal, to sample the analog input signal, togenerate a second digital signal, to filter the second digital signalwith a second noise shaping transfer function, to generate a secondnoise-shaped digital output, and to generate the quantization errorsignal based on a comparison of the analog input signal and the secondnoise-shaped digital output, wherein the second quantization stageincludes a successive approximation register (SAR) quantizer.
 4. Thecircuit of claim 3, wherein the quantization error signal is determinedbased on a residue voltage produced by the SAR quantizer duringgeneration of the second noise-shaped digital output.
 5. The circuit ofclaim 3, wherein the second quantization stage is configured to filterthe second digital signal using a loop filter with the secondnoise-shaping transfer function.
 6. The circuit of claim 3, furthercomprising: a second digital filter configured to filter the secondnoise-shaped digital output with an equivalent signal transfer functionand to generate a second stage digital output; and a combination circuitconfigured to combine the first stage digital output and the secondstage digital output and to generate a digital analog-to-digitalconversion (ADC) output signal with a second-order noise-shapingcharacteristic, wherein the combination circuit is an adder circuit. 7.The circuit of claim 3, wherein the second quantization stage is furtherconfigured to delay the quantization error signal by a clock cycle, togenerate a delayed quantization error signal, and to subtract thedelayed quantization error signal from the analog input signal in afeedback loop.
 8. The circuit of claim 1, wherein the first quantizationstage is configured to receive an inversion of the quantization errorsignal.
 9. The circuit of claim 1, wherein the first quantization stageis configured to filter the first digital signal with a firstnoise-shaping transfer function that approximates a first-orderdifference operation.
 10. A circuit comprising: a first quantizationstage configured to generate a quantization error signal; and a secondquantization stage configured to receive the quantization error signal,to sample the quantization error signal, to generate a second digitalsignal, to filter the second digital signal, and to generate a secondnoise-shaped digital output.
 11. The circuit of claim 10, wherein: thefirst quantization stage is further configured to receive an analoginput signal, to sample the analog input signal based on a first inputclock signal, to generate a first digital signal, to filter the firstdigital signal with a first noise-shaping transfer function, to generatea first noise-shaped digital output, and to generate the quantizationerror signal based on a comparison of the analog input signal and thefirst noise-shaped digital output; and the second quantization stage isconfigured to sample the quantization error signal based on a secondinput clock signal that has a higher frequency than the first inputclock signal and to filter the second digital signal with a secondnoise-shaping transfer function, the circuit further comprising: adigital up-sampler configured to increase a sampling rate of the firstnoise-shaped digital output by an amount proportional to a ratio of thesecond input clock signal and the first input clock signal and togenerate an up-sampled digital output; a first digital filter configuredto filter the up-sampled digital output with an equivalent signaltransfer function and to generate a first stage digital output; a seconddigital filter configured to filter the second noise-shaped digitaloutput with the first noise-shaping transfer function and to generate asecond stage digital output with a second-order noise-shapingcharacteristic; and a combination circuit configured to combine thefirst stage digital output and the second stage digital output and togenerate a digital analog-to-digital conversion (ADC) output signal withthe second-order noise-shaping characteristic.
 12. The circuit of claim10, wherein the second quantization stage includes an open loop voltagecontrolled oscillator (VCO)-based quantizer.
 13. The circuit of claim10, wherein the first quantization stage includes a successiveapproximation register (SAR) quantizer.
 14. The circuit of claim 10,wherein the second quantization stage is configured to receive aninversion of the quantization error signal.
 15. A method comprising:filtering a first noise-shaped digital output with an equivalent signaltransfer function to generate a first stage digital output; filtering asecond noise-shaped digital output with a first noise-shaping transferfunction to generate a second stage digital output; and combining thefirst stage digital output and the second stage digital output togenerate a digital analog-to-digital conversion (ADC) output signal. 16.The method of claim 15, further comprising: receiving an analog inputsignal at a first quantization stage; sampling the analog input signalat the first quantization stage to generate a first digital signal;filtering the first digital signal with the first noise-shaping transferfunction to generate the first noise-shaped digital output; generating aquantization error signal at the first quantization stage based on acomparison of the analog input signal and the first noise-shaped digitaloutput; receiving the quantization error signal at a second quantizationstage; sampling the quantization error signal to generate a seconddigital signal; and filtering the second digital signal with a secondnoise-shaping transfer function to generate the second noise-shapeddigital output, wherein the second stage digital output and the digitalADC output signal are generated with a second-order noise-shapingcharacteristic and the first quantization stage includes a successiveapproximation register (SAR) quantizer.
 17. The method of claim 16,further comprising determining the quantization error signal based on aresidue voltage produced by the SAR quantizer during generation of thefirst noise-shaped digital output.
 18. The method of claim 16, whereinthe second quantization stage is configured to receive an inversion ofthe quantization error signal.
 19. The method of claim 16, wherein thesecond noise-shaping transfer function approximates a first-orderdifference operation.
 20. The method of claim 16, further comprising:delaying the quantization error signal by a clock cycle to generate adelayed quantization error signal; and subtracting the delayedquantization error signal from the analog input signal in a feedbackloop.